Overvoltages may be due to antenna effects. This is because, during etching, essentially plasma etching, of the conducting tracks in the BEOL (back end of line) part, which are typically made of metal, the plasma tends to electrically charge the lines etched, all the more so if these lines are of substantial size. Such a line then forms an antenna for a structure, for example a capacitor, which is connected to it and the charges accumulated in the antenna during the etching may drain via the structure, at the risk of damaging it.
These overvoltages may also be due to various charge accumulations caused for example by friction, between flows of liquids or gases and the surfaces of the semiconductor wafers, and also during manual or automatic handling of the wafers.
In CMOS, MOS, BiCMOS technologies especially, these metal lines are often connected to thin oxides able to withstand only very low voltages (typically less than 5 volts for a CMOS logic technology at less than 0.18 microns). In the case of overvoltages, if no precautions are taken, the draining of the resulting current occurs through the oxides causing them to weaken or even break down.
The reliability of the integrated circuits is therefore affected, especially by output losses and faults, gate-oxide breakdown for example.
The reliability of the test structures for testing these integrated circuits is also affected. These test structures, which are for example placed on the scribe lines of the semiconductor wafers, comprise for example capacitive components, the dielectrics (oxides) of which are representative of those present in the components of the integrated circuit. These test structures thus serve for measuring the quality of the oxides. However, if these test structures have been subjected to overvoltages, the test results will be false.
To prevent this type of problem, measures may be taken during the design phase and during fabrication.
In the design phase, it is endeavored to detect structures at risk with regard to antenna effects. These structures are typically those having a small number of connected junctions relative to the length of the line to which the junctions are connected. The aim is therefore to modify these structures (size/shape, intentional addition of diodes) so as to reduce the ratio of the length to the number of diodes.
During fabrication, particular precautions are taken, especially in the use of etching plasmas and ionized liquids.
The test structures sometimes have a specific characteristic, in particular when they comprise capacitive components. This is because it is necessary to be able to apply, across the terminals of the capacitive component or components, a test voltage equal to the breakdown voltage of the dielectric of the capacitive component. Moreover, if the component is protected from overvoltages by a diode, the latter must have a threshold at least equal to this breakdown voltage. But in this case the diode no longer protects the capacitive component.
An incompatibility therefore presents itself since either the structure is protected from overvoltages and it is not possible to fully test the structure, or it is possible to fully test the structure, by applying a voltage equal to the oxide breakdown voltage, and the structure is then no longer protected from overvoltages.